Advanced Integrated Circuits (IC) fabrication processes, in their quest for integration density, high performance, reliable circuits, and low power, have recently taken a step to lower the voltage of the power supply needed to run the IC chips. Lowering this voltage allows the fabrication process to have smaller geometries and better performance without compromising the reliability or the quality of the integrated circuits.
One consequence of using the lower power supply voltage is the susceptibility of input and output pads to damage from external voltages higher than the power supply of the IC. This situation often occurs when an external device, which operates at a higher power supply voltage and which is electrically coupled to the input/output pad, drives the pad to a greater voltage than the power supply of the IC. The situation can also occur from transient spikes on the power supply of the IC. Damage results if excessive voltages occur across any two of the three terminals of the transistor (Gate, Source, Drain).
In addition, damage results to the gate oxide of a transistor due to hot carrier injection if it is allowed to draw large amounts of current from its drain to its source. Excessive voltages introduced across the source and drain of the transistor when the transistor is on allows excessive current to flow and results in permanent damage to the transistor.
A contextual example of the above situation may be seen in the migration of integrated circuits from 5 volts to 3.3 volts. As this migration takes place, applications are being built that have both 5 volts and 3.3 volts driving the same bus. This is possible since the logic levels driving and received by 5 volt and 3.3 volt chips are usually the same. For example, both 5 volt and 3.3 volt chips consider a logic "1" to be any voltage above 2.4 volts, while a logic "0" is any voltage below 0.4 volts. As a result of mixed IC applications, however, ICs powered by 3.3 volt sources need to be tolerant to the 5 volt signals. Since these signals can also be very high speed signals, the 3.3 volt chips must also be tolerant of the increased transmission line spikes and reflections caused by the increased speed.